With the continuous trend of reducing feature sizes, and employing continuously smaller components on integrated circuits, new challenges arise on the way of silicon CMOS circuits and devices. Emerging “nanodevices” promise the possibility of increased integration density and reduced power consumption. The emerging and new devices, partially due to their extremely small dimensions, show large variations in their behaviour. The variation shown by these devices affects their reliability and the performance of circuits made from them. The Carbon Nano-Tube (CNT) is one such device which is also the device of choice in this work. This work is concerned with building reliable systems out of these unreliable components. The work was done in HSPICE with the help of the Stanford CNFET model. Logic gates are implemented using CNT Field Effect Transistors (CNFETs) which are in turn made from CNTs with different physical attributes. Given a CNT manufacturing process, there exists a mean and standard deviation (STD) for the diameter distribution of the manufactured CNTs which depend on the accuracy of the manufacturing process.

In the first part of this work, CNTs with different mean diameters and standard deviations (STD) in their diameter distribution are considered. Simulation results show that logic gates made from CNTs with larger mean and smaller STDs in their diameter distribution show less variation in their timing behaviour (propagation delay, rise and fall times) and a promise of more reliable operation.
Alternative structures were then explored in the form of multiplexers and XOR gates. It is shown that these structures have the advantage over the gates studied previously in that they exhibit similar rise and fall transition times and hence are better suited to CNFET-based circuit design.
The next stage of this work involves implementation and simulation of a memory structure (SRAM). Parameters such as Static Noise Margin (SNM), leakage power and read/write delays were studied and the effects of CNT diameter variation on them examined.
The next contributions of this work are empirical models developed for a library of CNFET-based logic gates/circuit structures. The models can predict both the mean and standard deviation (STD) in various circuit performance parameters of a given CNFET-based logic gate/SRAM given the mean and STD of the diameter of CNTs used in their manufacture. The aim is, given a target reliability specification (timing requirements, power, speed, etc.), for various logic gates, and larger circuit components, to come up with a design strategy to suggest what physical properties the nano-device of choice should have to meet the target specification or vice versa. Best-case CNT diameter mean and STD selection scenarios are proposed to minimise circuit parameter variations.
In the last part of this work, the effects of doping fluctuations in the source/drain regions of the CNFETs on the performance of logic gates made from them are studied. The work concludes that if doping concentration is kept above 1%, variation in doping concentration has a minimal effect on performance parameters